Qualcomm takes RISC on Arm alternative with Ventana buy

"Ventana's Veyron V2 chiplet design features up to 32 RISC-V RVA23-compatible CPU cores clocked at up to 3.85 GHz, and is equipped with up to 1.5 MB of L2 cache per core and 128 MB of shared L3 cache. Each core is equipped with both a 512-bit vector unit based on the RVV 1.0 spec, and a custom matrix math accelerator for AI and machine learning applications. According to Ventana, the matrix unit is good for 0.5 TOPS (INT8) per GHz per core."

"However, the acquisition of Ventana points to the possibility of a far more potent class of RISC-V processors from Qualcomm. Qualcomm is no stranger to RISC-V. The company has been toying with the instruction set architecture (ISA) for years now. The chipset giant has been using RISC-V microcontrollers in its SoCs going back to the Snapdragon 865 launched in 2019. In 2023, the company launched a collaboration with Google to bring low-power, high-performance RISC-V-based chips to wearables."

Qualcomm acquired Ventana Micro Systems, founded in 2018, which developed high-performance RISC-V CPU designs for datacenter and enterprise use. Qualcomm intends to continue developing Ventana's RISC-V designs in parallel with its custom Arm-based Oryon cores used in Snapdragon X-series chips. Ventana's Veyron V2 chiplet supports up to 32 RISC-V RVA23-compatible cores at up to 3.85 GHz, with up to 1.5 MB L2 per core and 128 MB shared L3, 512-bit RVV 1.0 vector units, and a custom matrix accelerator rated at 0.5 TOPS (INT8) per GHz per core. Qualcomm previously integrated RISC-V microcontrollers in SoCs and collaborated with Google on RISC-V wearables.

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